Recent research has unveiled a novel attack technique that manipulates a computer’s memory controller to circumvent some of the most robust hardware security boundaries in modern processors. This method targets critical areas such as System Management Mode (SMM), the Platform Security Processor (PSP), and CPU microcode.
Security researcher Christopher Domas introduced this technique through an open-source project named ‘skitter-creek-bath-salts’ on GitHub. The attack focuses on the DRAM controller’s address-translation logic, a fundamental layer beneath most existing defense mechanisms. Every physical address generated by the CPU passes through this controller, which remaps it into specific memory coordinates within the DIMM.
Security features like AMD’s Secure Encrypted Virtualization (SEV), Intel’s Software Guard Extensions (SGX), Intel’s Trust Domain Extensions (TDX), ARM’s TrustZone, and firmware-based memory carveouts depend on the assumption that physical addresses remain fixed and predictable once they exit the CPU core. Domas’s research demonstrates that this assumption can be invalidated with a single instruction.
DRAM Scrambling Attack
By altering specific configuration bits in the memory controller, an attacker can modify how physical addresses map onto actual DRAM cells, effectively ‘spaghettifying’ memory. This remapping allows a different address to point to the same physical memory cell that was previously inaccessible.
Since access-control mechanisms above the memory controller verify physical addresses rather than the underlying DRAM coordinates, they fail to detect changes in the memory map. This vulnerability is not tied to a single flaw that can be patched; it exploits the linear nature of the address transformation performed by the memory controller, which can be mathematically reconstructed using linear algebra and tools like the Z3 SMT solver, even when the remapping details are undocumented.
Domas demonstrated this technique on AMD Family 16h processors, extracting the fTPM’s RSA signing routine directly from PSP memory, which is intended to be isolated from the operating system. He also accessed the SMM interrupt handler from SMRAM, a region marketed as ‘locked’ by the chipset, and retrieved raw CPU register states, including page-table roots and APIC configurations, stored in DRAM during low-power idle states.
Notably, the research reveals that a CPU’s active microcode patch, typically volatile and inaccessible, is temporarily written to DRAM during idle transitions. This patch can be both read and overwritten using the same aliasing technique.
While the proof-of-concept targets an older AMD platform with documented controller registers, Domas notes that similar architectural patterns—such as channel and rank interleaving, bank swizzling, and chip-select mapping—exist across virtually all modern memory controllers, including those from AMD, Intel, ARM, and RISC-V.
These findings will be presented in detail at Black Hat 2026. The research community is expected to closely monitor how chipmakers address this class of vulnerabilities, which lie beyond the reach of traditional CPU security models.
This development underscores the evolving nature of hardware vulnerabilities and the need for continuous innovation in security measures. As attackers delve deeper into system architectures, it becomes imperative for hardware and software developers to collaborate on designing more resilient systems that can withstand such sophisticated attacks.
