AMD has recently identified a series of vulnerabilities, collectively termed Transient Scheduler Attacks (TSA), impacting a wide array of its processors. These vulnerabilities exploit specific microarchitectural conditions to execute speculative side-channel attacks, potentially leading to unauthorized data access.
Understanding Transient Scheduler Attacks
Transient Scheduler Attacks are a novel class of speculative side-channel vulnerabilities that leverage the execution timing of instructions under certain microarchitectural scenarios. In these instances, attackers can analyze timing discrepancies to infer data from other contexts, resulting in potential information leakage. This type of attack is reminiscent of previous vulnerabilities like Meltdown and Spectre, which similarly exploited speculative execution to access sensitive data.
Discovery and Disclosure
The TSA vulnerabilities were uncovered during a collaborative study by Microsoft and ETH Zurich researchers. Their research focused on testing modern CPUs against speculative execution attacks by examining the isolation between security domains such as virtual machines, kernels, and processes. Following responsible disclosure in June 2024, AMD assigned the following CVE identifiers to the vulnerabilities:
– CVE-2024-36350 (CVSS score: 5.6): This vulnerability allows an attacker to infer data from previous stores, potentially leading to the leakage of privileged information.
– CVE-2024-36357 (CVSS score: 5.6): An attacker can infer data in the L1D cache, which may result in the leakage of sensitive information across privileged boundaries.
– CVE-2024-36348 (CVSS score: 3.8): This issue permits a user process to speculatively infer control registers, even if the UMIP feature is enabled, potentially leading to information leakage.
– CVE-2024-36349 (CVSS score: 3.8): A user process can infer TSC_AUX, even when such a read is disabled, potentially resulting in information leakage.
Technical Details
The TSA vulnerabilities exploit a phenomenon known as false completion. This occurs when the CPU hardware anticipates that load instructions will complete swiftly, but certain conditions prevent their successful completion. As a result, dependent operations may be scheduled for execution before the false completion is detected. Since the load did not actually complete, the data associated with that load is considered invalid. The load will be re-executed later to complete successfully, and any dependent operations will re-execute with the valid data when it is ready.
AMD has identified two primary variants of TSA:
1. TSA-L1: This variant targets errors in how the L1 cache handles microtag lookups. The CPU may incorrectly believe data is present in the cache when it isn’t, leading to the loading of incorrect data that an attacker could then infer.
2. TSA-SQ: This variant occurs when load instructions erroneously retrieve data from the store queue due to the unavailability of required data. In such cases, incorrect data can be detected by an attacker and used to infer sensitive information from previously executed operations, even if they were executed in a different context.
Affected Processors
A wide range of AMD processors are susceptible to TSA vulnerabilities, including:
– 3rd and 4th Generation AMD EPYC Processors: These data center chips are integral to cloud and on-premises infrastructure.
– AMD Ryzen Series Processors: Deployed across corporate workstations and consumer devices, these processors are prevalent in various computing environments.
– AMD Instinct MI300A: Designed for high-performance computing and AI workloads, this processor is also affected.
– AMD Ryzen Threadripper PRO 7000 WX-Series Processors: Targeted at professional workstations, these processors are included in the list of affected models.
– AMD Ryzen Embedded Processors: Utilized in embedded systems, these processors are also vulnerable.
Severity Ratings and Industry Response
AMD has rated the vulnerabilities with CVSS scores ranging from 3.8 to 5.6, categorizing them as medium to low severity. However, cybersecurity firm CrowdStrike has independently classified certain flaws, specifically CVE-2024-36350 and CVE-2024-36357, as critical threats. CrowdStrike’s assessment emphasizes the potential for privilege escalation and security mechanism bypass, particularly in environments where attackers may have already gained initial system access through malware, supply chain compromises, or insider threats.
Mitigation Measures
AMD has released microcode updates to address the TSA vulnerabilities. These updates have been provided to Original Equipment Manufacturers (OEMs) and are being coordinated with operating system vendors to ensure comprehensive mitigations. The Linux kernel has also integrated mitigation logic for TSA, introducing a new MITIGATION_TSA configuration option and a tsa= tunable for adjusting the TSA mitigation behavior on AMD CPUs.
System administrators are advised to update to the latest firmware and operating system versions to protect against these vulnerabilities. It’s important to note that while these attacks are complex and require local access to the machine, the potential for information leakage underscores the necessity of applying these updates promptly.
Conclusion
The disclosure of Transient Scheduler Attacks highlights the ongoing challenges in securing modern processors against speculative execution vulnerabilities. While AMD has taken steps to mitigate these issues through microcode and software updates, the situation underscores the importance of continuous vigilance and prompt application of security patches to safeguard sensitive information.